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rev. 1.0 11/11 copyright ? 2011 by silicon laboratories SI3462 SI3462 s ingle -p ort ieee 802.3 at p o e/p o e+ pse i nterface features applications description the SI3462 is a single-port power ma nagement controller for ieee 802.3at- compliant power sourcing equipment (pse). the SI3462 can be powered from a 50 v input using a shunt regulator, or, to save power, it can be powered from 50 v and 3.3 v power supplies. the ieee-required powered device (pd) detection feature uses a robust 3-point algorithm to avoid false detection events. the SI3462's refe rence design kit also provides full ieee-compliant classification and pd disconnect. intelligent protection circuitry includes input under-voltage lockout (uvlo), classifi cation-based current limiting, and output short-circuit protection. the SI3462 is designed to operate completely independently of host processor control. an led status signal is provided to indicate the port status, including de tection, power good, and output fault event information. the SI3462 is pin-programmable to support four available power levels, endpoint and mid-span applications, and auto-retry or restart after disconnect functions. a comprehensive reference design kit is available (SI3462-evb), including a complete schematic and bill of materials. the SI3462 also features no-classify modes, for circumstances where detection is desired but classification step s can be skipped. example applications include dedicated, point-to-point conne ctions for ip cameras, point-of-sale terminals, and wireless access points where the application power requirements are well understood. these modes allow elimination of classification-related components from the bill of materials. ? ieee 802.3at tm compliant pse ? autonomous operation requires no host processor interface ? complete reference design available, including SI3462 controller and schematic: ?? low-cost bom ?? compact pcb footprint ?? operates directly from a +50 v isolated supply ?? supports up to 30 w maximum output power (class 4) ?? robust 3-point detection algorithm eliminates false detection events ?? ieee-compliant disconnect ?? inrush current control ?? short-circuit output fault protection ?? led status signal (detect, power good, output fault) ? unh interoperability test lab report available ? extended operating range (C40 to +85 c) ? 11-pin quad flat no-lead (qfn) package ?? tiny 3x3 mm pcb footprint; rohs-compliant ? no-classify modes force power after valid detection ?? eliminates 10 bom components ? ieee 802.3at en dpoints and midspans ? environment a and b pses ? embedded pses ? set-top boxes ? ftth media converters ? cable modem and dsl gateways pin assignments 11-pin qfn (3x3 mm) top viewpads on bottom of package isense status vsense rst deta 1 2 3 4 5 10 9 8 7 6 dc1 clsmark dc2 vdd clsmode gnd SI3462 11 11 11 11
SI3462 2 rev. 1.0
SI3462 rev. 1.0 3 t able of c ontents section page 1. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. SI3462 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1. SI3462-evb perform ance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2. pse timing charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. typical SI3462-evb wavef orms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. SI3462-evb functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.2. operating mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. operating mode sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1. detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2. classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.3. power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.4. overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5. disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5.6. uvlo and ovlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.7. status led function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1. isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2. external component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3. input dc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 7. SI3462 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. package outline: 11-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. solder paste mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 10.1. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 11.1. SI3462 top marking (qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SI3462 4 rev. 1.0 1. typical application schematic figure 1. SI3462 typical application schematic SI3462 gnd deta v dd +3.3v v out 48 v pse output (to port magnetics) rst vdd detect & mark isense gnd status clsmode dc1 clsmark vsense detect fault pgood dc2 note: refer to the SI3462-evb user guide for complete schematic details v in +50v gnd + - +50v classification (optional) and gate drive optional 3.3v regulator
SI3462 rev. 1.0 5 2. electrical specifications the following specifications apply to the SI3462 controller. refer to tables 3 and 6 and the SI3462-evb user's guide and schematics for additional details about the electr ical specifications of the SI3462-evb reference design. table 1. recommended operating conditions description symbol test conditions min typ max unit operating temperature range t a C40 25 +85 c thermal impedance ? ja no airflow 75 c/w vdd input supply voltage vdd during all operating modes (detect, classification, disconnect) 2.7 3.3 3.6 v table 2. electrical characteristics* description symbol test conditions min typ max unit digital pins: clsmark, dc1, dc2, cl smode, status (output mode), rst output high voltage v oh i oh =C3ma i oh =C10a 0.7 x vdd vdd C 0.1 v output low voltage v ol i ol =8.5ma i ol =10a 0.6 0.1 v input high voltage v ih any digital pin 0.7 x vdd v input low voltage v il any digital pin 0.6 v input leakage current i il v in =0v 1 a analog pins: isense, vsense, deta, status (input mode) input capacitance 5pf input leakage current i il 1a *note: vdd = 2.7 to 3.6 v, C40 to +85 c unless otherwise specified.
SI3462 6 rev. 1.0 2.1. SI3462-evb perf ormance characteristics when implemented according to the recommended exter nal component and layout guidelines for the SI3462-evb, the SI3462 enables the following performance specifications in single-port pse applicatio ns. refer to the SI3462- evb user's guide and sc hematics for details. table 3. selected electrical specifications (SI3462-evb) description symbol test conditions min typ 1 max unit power supplies v in input supply range v in C40 to +85 c ambient range 45 50 57 v v in input uvlo voltage uvlo uvlo turn-off voltage at v in 4 24 5 v v in input ovlo voltage ovlo ovlo turn-off voltage at v in 57 60 v vdd supply voltage range v dd SI3462 supply voltage range 3.15 3.3 3.45 v output supply voltage v out pse output voltage at v in = 50 v and i out = 350 ma 4 9v supply current i in current into the v dd node (not including shunt regulator) 8.0 10.5 ma detection specifications detection voltage v det detection point 1 detection point 2 detection point 3 4 . 0 8.0 4.0 v detection current i det short circuit 3 ma minimum signature resistance r detmin 15 17 19 k ? maximum signature resistance r detmax 26.5 29 33 k ? classification specifications 5 classification voltage v class 0ma < i class < 45 ma 15.5 20.5 v classification cur- rent limit i class measured with 100 ? across v out 55 75 95 ma notes: 1. typical specifications are based on an ambient operating temperature of 25 c and vin = +50 v unless otherwise specified. 2. absolute classification current limits are configurable. see 5.2. classification and "5.3. power-up" on page 14. 3. typical icut values are adjusted according to the input vo ltage to provide power limiting with approximately 5% margin against the 802.3 requirements. the maximum icut values are consistent with the i eee requirement that icut maximum is less than 400 ma at the minimum allowed vout of 44 v or 684 ma for poe+ mode at the minimum allowed vout of 50 v. 4. overload current is within limits, typically in less than 1 ms. 5. classification is optional in some operating modes. refer to table 6 for operating modes. 6. classification mark is only required for type 2/class 4 support
SI3462 rev. 1.0 7 classification current region i class _ region class 0 0 5 ma class 1 8 13 ma class 2 16 21 ma class 3 25 31 ma class 4 35 45 ma mark voltage 6 v mark 78 . 51 0v mark current 6 i mark_lim short circuit 9 ma protection and current control overload current threshold 2,3 i cut class 0 and class 4 poe 15,400/v out 16,170/v out 17,600/v out ma class 1 4,000/v out 4,200/v out 4,600/v out ma class 2 7,000/v out 7,350/v out 8,000/v out ma class 3 15,400/v out 16,170/v out 17,600/v out ma class 4 poe+ 30,000/v out 31,500/v out 34,200/v out ma overload current limit 4 i lim class 0/1/2/3 and class 4 poe; output = 100 ? across v out 400 425 450 ma i lim poe+ class 4 poe+; output = 50 ? across v out 684 750 825 ma overload time t lim class 0/1/2/3 and class 4 poe; output = 100 ? across v out 50 60 75 ms class 4 poe+; output = 50 ? across v out 14 17 20 ms disconnect current i min disconnect current 5 7.5 10 ma efficiency system efficiency ? (p in @ v in ) to (p out @ v out ) 93 % table 3. selected electrical specifications (SI3462-evb) (continued) description symbol test conditions min typ 1 max unit notes: 1. typical specifications are based on an ambient operating temperature of 25 c and vin = +50 v unless otherwise specified. 2. absolute classification current limits are configurable. see 5.2. classification and "5.3. power-up" on page 14. 3. typical icut values are adjusted according to the input vo ltage to provide power limiting with approximately 5% margin against the 802.3 requirements. the maximum icut values are consistent with the i eee requirement that icut maximum is less than 400 ma at the minimum allowed vout of 44 v or 684 ma for poe+ mode at the minimum allowed vout of 50 v. 4. overload current is within limits, typically in less than 1 ms. 5. classification is optional in some operating modes. refer to table 6 for operating modes. 6. classification mark is only required for type 2/class 4 support
SI3462 8 rev. 1.0 table 4. thermal characteristics description symbol test conditions min typ max unit thermal impedance ? ja no airflow 75 c/w junction temperature tj C40 125 c table 5. absolute maximum ratings* parameter conditions max rating unit ambient temperature under bias C55 to +125 c storage temperature C65 to +150 c voltage on rst or any i/o pin with respect to gnd vdd > 2.2 v C0.3 to 5.8 v voltage on vdd with respect to gnd C0.3 to 4.2 v maximum total current through vdd and gnd 500 ma maximum output current into clsmark, dc1, dc2, clsmode, status, isense, rst, vsense, deta (any i/o pin) 100 ma esd tolerance human body model C2 kv to +2 kv v lead temperature soldering, 10 seconds maximum 260 c *note: stresses above those listed in this table may cause permanent device damage. this is a stress rating only, and functional operation of the devices at thes e or any conditions above those indicat ed in the operational listings of this specification is not implied. exposure to maximum rating cond itions for extended periods may affect device reliability.
SI3462 rev. 1.0 9 2.2. pse timing characteristics when implemented in accordance with the recommended ex ternal components and layout guidelines, the SI3462 controller enables the followi ng typical performance characteristics in single-port pse applicat ions. refer to the SI3462-evb applications note, schematics, and user's guide for more details. table 6. pse timing description symbol test conditions min typ max unit endpoint detection delay cycle t det_cycle time from pd connection to port to completion of detection process. 90 460 ms detection time t detect time required to measure pd signature resistance. 90 ms classification delay cycle t class_cycle class 0/1/2/3; time from successful detect mode to classification complete. 60 ms class 4, two event classification; time from successful detect mode to classification complete. 99 ms classification time t class class 0/1/2/3 and class 4 poe; 30 ms class 4 poe+ 69 ms power-up turn-on delay t pwrup class 0/1/2/3 and class 4 poe; time from when a valid detection is completed until v out power is applied 76 ms class 4 poe+; time from when a valid detection is completed until v out power is applied 112 ms midspan detect back- off time t bom 2.0 s error delay time t ed time from error to restart of detec- tion in auto-restart mode. 2.0 s disconnect delay t dc_dis 350 ms note: these typical specifications are based on an ambient operating temperature of 25 c and v in =+50v.
SI3462 10 rev. 1.0 3. typical SI3462-evb waveforms note: voltages are negative going with respect to the positive input. figure 2. typical SI3462-evb waveforms ch1: poe output voltage referenced to the +50v rail detection classification power-on ch1: poe output voltage referenced to the +50v rail detection power-on two event classification mark pulse ch1: poe output voltage referenced to the +50v rail t detect g powering a poe+ device powering a poe device detection time ch1: poe output voltage referenced to the +50v rail detection classification t pwrup t class_cycle ch1: poe output voltage referenced to the +50v rail detection classification t pwrup t class_cycle t bom classification and power-up delay poe+ classification and power-up delay poe midspan backoff after bad classification result poe+ current limit response poe current limit response overload during classification t lim poe+ i lim poe+ t lim poe i lim poe i class
SI3462 rev. 1.0 11 4. SI3462-evb functional description in combination with low-cost exter nal components, the SI3462 controller provides a co mplete pse solution for embedded poe applicat ions. the SI3462-evb re ference design o perates from a +50 v is olated power supply and delivers power to the powered device. refer to the SI3462-evb user's guide and schema tics for descriptions in the following sections. the basic sequence of applying power is shown in figure 3. following is the description of the function that must be performed in each phase. figure 3. basic power-up sequence t det_cycle t class_cycle t pwrup -2.8v -15.5v -10v -20.5v -44v -57v ch1: poe output voltage referenced to the +50v rail detection classification power-on
SI3462 12 rev. 1.0 4.1. reset state at power-up or if reset is held low, the SI3462 is in an inactive state with the pass fet q4 off. 4.2. operating mode configuration at power-up, the SI3462 reads the voltage on the status pi n, which is set by a dip switch and a resistor network. the status pin voltage level configures all of th e SI3462's operating modes as summarized in table 7. table 7. operating modes 1,2,3,4,5 status pin voltage (v) operating mode pse type midspan/ endpoint restart action on fault or overload event condition available power classification bom 5 classification mark bom 5 < 0.122 2 midspan restart after disconnection 30 w no no 0.122 to 0.338 1 midspan restart after disconnection 7w yes no 0.338 to 0.548 1 midspan restart after disconnection 15.4 w no no 0.548 to 0.756 2 midspan restart after disconnection 30 w yes yes 0.756 to 0.961 2 midspan auto restart after 2 s 30 w no no 0.961 to 1.162 1 midspan auto restart after 2 s 7 w yes no 1.162 to 1.366 1 midspan auto restart after 2 s 15.4 w no no 1.366 to 1.575 2 midspan auto restart after 2 s 30 w yes yes 1.575 to 1.784 2 endpoint restart after disconnection 30 w no no 1.784 to 1.990 1 endpoint restart after disconnection 7w yes no 1.990 to 2.196 1 endpoint restart after disconnection 15.4 w no no 2.196 to 2.407 2 endpoint restart after disconnection 30 w yes yes notes: 1. after power-up, the status pin drives the base of an npn transistor that controls an led. 2. there is a trade-off in selecting the mode setting resistor values between voltage step accuracy and additional worst- case supply current. for high-value resistors, the base current will alter the voltage steps while low-value resistors may place higher load on the status pin while driving the led. the suggested resulting parallel resistance used by the SI3462-evb is 2.0 k ? . 3. each mode setting resistor should be connected either to gnd or +3.3 v through the dip switch. care should be taken not to short the +3.3 v supply to gnd. 4. a reset is required after a dip switch position change for the new mode to take effect. 5. refer to the SI3462-evb user guide to understand the components required to support classification and mark.
SI3462 rev. 1.0 13 2.407 to 2.618 2 endpoint auto restart after 2 s 30 w no no 2.618 to 2.838 1 endpoint auto restart after 2 s 7 w yes no 2.838 to 3.044 1 endpoint auto restart after 2 s 15.4 w no no >3.044 2 endpoint auto restart after 2 s 30 w yes yes table 7. operating modes 1,2,3,4,5 (continued) status pin voltage (v) operating mode pse type midspan/ endpoint restart action on fault or overload event condition available power classification bom 5 classification mark bom 5 notes: 1. after power-up, the status pin drives the base of an npn transistor that controls an led. 2. there is a trade-off in selecting the mode setting resistor values between voltage step accuracy and additional worst- case supply current. for high-value resistors, the base current will alter the voltage steps while low-value resistors may place higher load on the status pin while driving the led. the suggested resulting parallel resistance used by the SI3462-evb is 2.0 k ? . 3. each mode setting resistor should be connected either to gnd or +3.3 v through the dip switch. care should be taken not to short the +3.3 v supply to gnd. 4. a reset is required after a dip switch position change for the new mode to take effect. 5. refer to the SI3462-evb user guide to understand the components required to support classification and mark.
SI3462 14 rev. 1.0 5. operating mode sequencing 5.1. detection after power-up the SI3462 enters the detection state wit h the pass fet off. prior to turning the fet on, a valid detection sequence must take place. according to the ieee specificat ions, the detection process consists of sensing a nominal 25 k ? signature resistance in parallel with up to 0.15 f of capacitance. to eliminate the possibility of false detection events, the SI3462-evb referenc e design performs a ro bust 3-point detection sequence by varying the voltage across the load that connects to the +50 v supply rail and returns to gnd via d3, q14, r26, and r37. r37 serves as a current sensing resistor, and the SI3462 monitors the volt age drop across it during the detection process. at the beginning of the detection sequence, v out is at zero; then, it is varied from 4 to 8 v and then back to 4 v for 20+20+50 ms at each respective level. if the pd's signature resistance is in the rgood range of 17 to 29 k ? , the SI3462 proceeds to classification and power-up. if the pd resistance is not in this range, the detection sequence repeats continuously. detection is sequenced approximately every 400 ms for endspan and 2.2 seconds for midspan configurations and repeats until rgood is sensed , indicating a valid pd has been detected. the status led (d2) is flashed at a rate of about 1.5 hz to indicate the pse is searching for a valid pd. 5.2. classification after a valid pd is detected, the pse in terrogates the pd to find its power requirement. this pr ocedure is called classification and may be carried out in different ways. the SI3462 implements the one-event classification for type1 pds and the two-event classification for type2 pds. for one-event classification, the pass fet q4 is turned on and programmed for an output voltage of 18 v with a current limit of 75 ma for 30 ms. for the two-event cl assification, the 18 v pulse is output twice with an 8.5 v amplitude mark pulse for 10 ms between the two classifica tion pulses. the current measured at the isense input during the classification process dete rmines the class level of the pd (refer to table 3 on page 6 for current ranges). if the SI3462-evb has 30 w of available po wer, it attempts to classify a type 2 pd first by the two-event method. if the detected class is other than class 4 or there is less th an 30 w of power available, the SI3462 tries to classify a type1 pd using the one-event method. if the class level of the pd is not within the supported r ange as set by the initial voltage on the SI3462's status pin (refer to the operating mode configuration section abov e), an error is declared, and the led blinks rapidly at a 10 hz rate. this is refe rred to as classification-based power denial. if the class level is in the supported range, the SI3462 proceeds to power-up. this is referred to as classification-based power granting. if the classification level is at a grea ter power than can be supported based on the voltage read by the status pin during start-up, an error condition is reported by flashing the led at a 10 hz rate for two seconds before the state machine goes back to the detection cycle. the SI3462 also features no-classify modes for circumstanc es where detection is desire d but classification steps can be skipped. example applications include dedicated, po int-to-point connec tions for ip cameras, point-of-sale terminals, and wireless access points where the application power requirements are well understood. these modes allow elimination of cl assification-related components from the bill of materials. please refer to the SI3462- evb user guide for further details. 5.3. power-up after successful classification, the pass fet is turned on wit h an initial current limit of 425 ma (for all pd classes), and the respective ilim values (indicated in table 3) take effect after the fet is fully turned on. after power-up is complete, power is applied to v out as long as there is not an overcurrent fault, disconnect, or input undervoltage (uvlo) or overvoltage (ovlo) condition. the stat us led is continuously lit when power is applied. if the output power exceeds t he level of the power requested during classification, the SI3462 will declare an error and shut down the port, flashing the led rapidly to indica te the error. depending on the initial voltage on the status pin, the SI3462 will wait either 2.2 seconds or until the pd has be en disconnected bef ore it enters the detection phase again to look for a valid load.
SI3462 rev. 1.0 15 5.4. overload protection the SI3462 implements a two-level overload protection scheme. the output current is limited to ilim, and the output is shut down if the current exceeds icut for more than 60 ms. if current limitation persists for more than 15 ms in case of poe+ class 4 loads, the output is shut down to protect the pass fet. current limit values are dynamically set according to the power level granted during the classification process and the effective output voltage (refer to table 3 on page 6 for current limit values). a special 425 ma current limit applies until the fet is fully tu rned on. if the fet does not fully turn on in the first 75 ms due to an overload condition, an error is decl ared. the maximum time that the 425 ma inrush current is supplied is about 70 ms due to a 5 ms period to initially ramp the fet gate voltage. the overload protection is implemented using a timer with a timeout set to 60 ms. if the output current exceeds the i cut threshold, the timer counts up; otherwise, if the output current drops below icut, the timer counts down towards zero at 1/16th the rate. if the timer reaches the se t timeout, an overcurrent fault is declared; the channel is shut down (by turning off the external pass fet), and the status led flashes rapidly at a rate of 10 hz. if the SI3462 was configured in the automatic restart mode during start-up, it will au tomatically resume the detection process after 2.2 seconds. in the restart after disconnect mode of operation, the status led will flash rapidly, and the SI3462 will not resume detectio n until it senses a resistance higher than 150 k ? . this condition can normally be achieved by removing the ethernet cable from the SI3462-evb's rj-45 jack la beled poe. then, the detection process begins; the status led blinks at a rate of 1.5 hz, and the SI3462 is allowed to go into classification and power-up mode if a valid pd signature resistance is detected. 5.5. disconnect the SI3462 implements a robust disconnect algorithm. if the output current level drops below 7.5 ma typical for more than 350 ms, the SI3462 declares a pd disconnect event, and the pass fet is turned off. the SI3462 automatically resumes the detection process after 500 ms. 5.6. uvlo and ovlo the SI3462-evb referenc e design is optimized for 50 v nominal input voltages (44 v minimum to 57 v maximum). if the input voltage drops below 42 v, a uvlo condition is declared, which generates the error condition (led flashing rapidly). an undervoltage event is a fault condition reported through the status led as a rapid blinking of 10 flashes per second. in the same way, if the input voltage exceeds 60 v, an ovlo condition is declared. in both cases, the output is shut down. the uvlo and ovlo conditions are continuously monitored in all operating states. 5.7. status led function during the normal detection sequence, the status led fl ashes at approximately 1.5 times per second as the detection process continues. after successful power up, the led glows continuously. if there is an error condition (i.e., class level is beyond programmed value or a fault or over current condition has been detected), the led flashes rapidly at 10 times per second. this occurs fo r two seconds for normal error delay, and the detection process will automatically start again after 2.2 s unless a restart after disconnect cond ition was set during the initial configuration. power will not be provided until an open circuit condition is detected. once the SI3462-evb detects an open circuit condition, the led blinks at 1.5 times per second. if the powered device (pd) is disconne cted so that a disconne ct event occurs, the led will start flashing at 1.5 times per second once the detect process resumes.
SI3462 16 rev. 1.0 6. design considerations 6.1. isolation the SI3462-evb's pse output power at vout is not isolated from the in put power source (vin). isolation of pse output power requires that the input be isolated from earth ground. typically , an ac-to-dc power supply is used to provide the 50 v power so the output of this supply is isolated from earth ground. 6.2. external component selection detailed notes on extern al component selectio n are provided in the SI3462-evb user's guide schematics and bom. in general, these recommendat ions must be followed closely to ensure output power stability, surge protection (surge protec tion diode), and overa ll ieee 802.3 compliance. 6.3. input dc supply the SI3462-evb reference design requires an isolated 50 v nominal dc input voltage (with a minimum of 44 v and a maximum of 57 v). the input power supply should be rated for at least 10% higher power level than the output power level chosen. this is primarily to account for the lo sses in the current-sensing resistor, t he pass fet, and the series protection diode of the SI3462-evb refe rence design. for example, to support a class 0 pse, th e input supply should be capable of supplying at least 16.94 w (15.4 w x 1.10 = 16.94 w). the power supply also needs to be able to source 425 ma for 60 ms for normal operation or 885 ma for 15 ms for high power (poe+) operation. the SI3462-evb reference design does not regulate the ou tput voltage during the power -on state; therefore, the input dc supply should meet the ripple and no ise specifications of the ieee 802.3 standard. the SI3462-evb refe rence design includes an option al 3.3 v shunt regulator that uses the 50 v input to generate the 3.3 v supply voltage for the SI3462 controller. alternatively, an external 3.3 v power source may be used.
SI3462 rev. 1.0 17 7. pin descriptions SI3462 pin functionality is described in table 8. note th at the information applies to the SI3462 device pins, while the SI3462-evb user's guide de scribes the inputs and output s of the evaluation system. refer to the complete SI3462-evb schematics and bom lis ting for information about the external components needed for the co mplete pse application circuit. table 8. SI3462 pin functionality pin # pin name pin type pin function 1 clsmark digital output logic high on this output increa ses the current capability of the detection circuitry while used for mark pulse generation. refer to the SI3462-evb schematics. if classi fication mark is not utilized, this signal is ignored. 2 dc1 digital output this is a pwm output providing the dc control voltage for the detection circuitry. it is also combined with the dc2 output in a ratio of 1:256 to provide the gate control voltage of the pass fet. 3 vdd power 3.3 v power supply input. 4 dc2 digital output this is a pwm output that (combined with the dc1 output) pro- vides the gate control voltage of the pass fet with high resolution. 5 clsmode digital output this is an open drain output. wh en high, it enables the feedback path controlling the 18 v classificati on voltage. if classification is not utilized, this signal is ignored. 6 deta analog input deta is an analog input pin. during the detection process, the dc1 pin duty cycle is varied to generate filtered dc voltages across the load, and the voltage drop across a current sensing resistor is measured through the deta input. 7 vsense analog input vsense is an analog inpu t used for sensing th e input dc voltage. 8rst digital input active low reset input. when low, it places the SI3462 device into an inactive state. when pulled high, the device begins the detec- tion process sequence. 9 isense analog input isense is an analog input connected to a current sense resistor for output current sensing. 11-pin qfn (3x3 mm) top viewpads on bottom of package isense status vsense rst deta 1 2 3 4 5 10 9 8 7 6 dc1 clsmark dc2 vdd clsmode gnd SI3462 11 11 11 11
SI3462 18 rev. 1.0 10 status analog in/digital out at power-up, the voltage on this pin is sensed to configure the pse available power, mid span/e nd span timing mode and the device's restart behavior when a fault condition is detected. refer to "4.2. operating mode configuration" on page 12. after reading the voltage present at this pin at power-up, the status pin becomes a digital output used to control an external led, which indicates when a detect, power good, or output fault condition has occurred. logic high turns the led on, and logic low turns the led off. refer to "5.7. status led function" on page 15. 11 gnd gnd ground connection for the SI3462. table 8. SI3462 pin functionality (continued) pin # pin name pin type pin function
SI3462 rev. 1.0 19 8. ordering guide ordering part number description package information temperature range (ambient) SI3462-e01-gm single-port pse controller 11-pin, 3 x 3 mm qfn. rohs compliant C40 to 85 c SI3462-evb SI3462 evaluation board and reference design kit evaluation board n/a notes: 1. add r to part number to denote tape-an d-reel option (e.g., SI3462-e01-gmr). 2. the ordering part number above is not the same as the device mark. see "11. top marking" on page 23 for more information.
SI3462 20 rev. 1.0 9. package outline: 11-pin qfn figure 4 illustrates the package details for the SI3462. table 9 lis ts the values for the di mensions shown in the illustration. the SI3462 is packaged in an industry-st andard, 3x3 mm, rohs-comp liant, 11-pin qfn package. figure 4. qfn-11 package drawing table 9. package diagram dimensions dimension min nom max a 0.80 0.90 1.00 a1 0.03 0.07 0.11 a3 0.25 ref b 0.18 0.25 0.30 d3 . 0 0 b s c . d2 1.30 1.35 1.40 e0 . 5 0 b s c . e3 . 0 0 b s c . e2 2.20 2.25 2.30 l .45 .55 .65 aaa 0.15 bbb 0.15 ddd 0.05 eee 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outl ine mo-243, variation veed except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
SI3462 rev. 1.0 21 10. solder paste mask figure 5. solder paste mask 0.50 mm lt e e d e lb k d2 b l d4 0 . 1 0 m m 0.50 mm 0.35 mm 0.30 mm 0.10 mm 0.20 mm 0.30 mm 0.20 mm 0.60 mm 0.70 mm d4 b 0.30 mm 0.35 mm e2 0.20 mm
SI3462 22 rev. 1.0 10.1. pcb land pattern figure 6. typical qfn-11 land diagram lt e e d e lb k b l d4 0 . 1 0 m m 0.50 mm 0.35 mm 0.30 mm 0.10 mm 0.20 mm d4 b 0.30 mm 0.20 mm e2 d2 0.10 mm
SI3462 rev. 1.0 23 11. top marking 11.1. SI3462 top marking (qfn) 11.2. top marking explanation line 1 marking: pin 1 identifier circle = 0.25 mm diameter product id 6201 62 = SI3462; 01 = firmware revision 01 line 2 marking: ettt = trace code assembly trace code e = product revision ttt = assembly trace code line 3 marking: yww = date code assigned by the assembly contractor. y = last digit of current year (ex: 2009 = 9) ww = current work week lead-free designator + 6201 ettt yww+
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